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The AMD Duron is AMD’s value-oriented Socket A processor family introduced in 2000 as a low-cost derivative of the original K7 Athlon, designed to deliver most of the Athlon’s core microarchitectural strengths at reduced manufacturing cost through a smaller L2 cache and mainstream platform positioning. Based first on the 0.18 µm Spitfire core and later on the 0.18 µm Morgan core, the Duron retains the K7 architecture’s superscalar, out-of-order execution engine, register renaming, speculative execution, strong floating-point unit, and EV6-derived double-data-rate front-side bus, while integrating a large 128 KiB split L1 cache and a reduced 64 KiB on-die L2 cache compared with contemporary Athlon models. Morgan-based versions also added SSE support and various power-management and data-prefetch refinements. Technically, the Duron is best understood as the budget branch of the early K7 family: architecturally much closer to the Athlon than Intel’s low-end alternatives often were to their higher-end counterparts, but differentiated primarily by cache size, bus speed, and market segment rather than by a fundamentally different core.